The present invention relates to a nonvolatile semiconductor memory in which data can be electrically rewritten using nonvolatile transistors.
A well-known nonvolatile semiconductor memory in which data can be electrically rewritten is the E.sup.2 PROM (Electrically Erasable and Programmable Read Only Memory). While E.sup.2 PROMs can have any of a number of different memory cell structures, most, however, tend to be of floating gate type structure, in which a floating gate electrode partially overlaps a diffusion layer, through a thin insulating film.
FIG. 1 is a sectional vie showing the structure of one such conventional memory cell. N-type diffusion layers 11, 12, and 13 are formed in a surface of p-type semiconductor substrate 10. Channel region 14 is formed between diffusion layers 11 and 12. Polysilicon electrode 16 is formed above channel region 14 and parts of diffusion layers 11 and 12. One portion of electrode 16 is thicker than the remainder thereof and is formed above diffusion layer 12. Insulation film 15 (described in detail later) is formed between substrate 10 and polysilicon electrode 16. This film 15 has thin insulation film 17 located between diffusion layer 12 and the thicker portion of electrode 16. In addition, polysilicon electrode 1 is formed above electrode 16 interposing insulating film 18 having a thickness almost equal to that of insulating film 15.
Channel region 20 i formed between diffusion layers 12 and 13. Polysilicon electrode 22 is formed above channel region 2 interposing insulating film 21 having a thickness almost equal to that of insulating film 15.
Diffusion layers 11 and 13 are respectively connected to source wiring S and bit line BL. Electrodes 16, 19, and 22 are respectively used as a floating gate electrode, a control gate electrode, and a gate electrode. Control gate electrode 19 and gate electrode 22 are connected to control gate line CG and selection gate line SG, respectively.
FIG. 2 is an equivalent circuit diagram of the conventional cell having the structure shown in FIG. 1. Transistor 41, as shown in FIG. 2, is of floating gate type. Diffusion layers 11 and 12 of transistor 41 are used as a source and a drain, respectively, transistor 41 itself constituting a memory transistor for storing data. Transistor 42 is of normal MOS type. Diffusion layers 12 and 13 of transistor 42 are used as a source and a drain, respectively, transistor 42 itself constituting a selection transistor for selecting memory transistor 41.
The operation modes of the above memory cell include data erase, write, and read modes. FIG. 3 is table which shows the voltages applied to source wiring S, bit line BL, control gate line CG, and selection gate line SG in each mode. There are three power-source voltages which can be applied in an integrated circuit incorporating an E.sup.2 PROM, i.e., ground power source voltage GND, read power source voltage Vcc, and write power source voltage Vpp. In ordinary operation, ground power source GND =0 V, read power source voltage Vcc =5 V, and write power source voltage Vpp =20 V. It should be noted that write power source voltage Vpp is not supplied by an external power source, but is generated in the integrated circuit itself by boosting read power source voltage Vcc.
The data erase mode, which is also known as the electron injecting mode, will now be described.
In the data erase mode, electrons are injected into floating gate electrode 16, to increase threshold voltage V.sub.TH of memory transistor 41. In the data erase mode, bit line BL =0 V, selection gate line SG =20 V, control gate line CG =20 V, and source wiring S =0 V. By setting selection gate line SG at 20 V, selection transistor 42 is rendered conductive, and the potential at n-type diffusion layer 12 becomes equal to that at bit line BL, i.e. 0 V. A high voltage is applied to floating gate electrode 16 from control gate line CG, and a high electric field is applied to thin insulating film 17 between floating gate electrode 16 and n-type diffusion layer 12. As a result, the electrons are injected into floating gate electrode 16 from n-type diffusion layer 12 by a tunnel current. As a result, threshold voltage V.sub.TH is increased up to, e.g., about 8 V.
The data write mode, also known as the electron discharge mode, will now be described.
In the data write mode, threshold voltage V.sub.TH of memory transistor 41 s decreased by discharging the electrons which were injected into floating gate electrode 16. In the data write mode, bit line BL =20 V, selection gate line SG =20 V, control gate line CG =0 V, and source wiring S =5 V. That is, the floating gate electrode 16 is set in a floating state. By setting selection gate line SG at 20 V, selection transistor 42 is rendered conductive and the potential at n-type diffusion layer 12 becomes equal to that at bit line BL, i.e., 20 V. A high electric field is applied to thin insulating film 17, in the opposite direction to that in the erase mode, the electrons are discharged from floating gate electrode 16 into n-type diffusion layer 1 by tunnel current. As a result, threshold voltage V.sub.TH of memory transistor 41 is decreased to, for example, -5 V.
In the data read mode, bit line BL =1 V, selection gate line SG =5 V, control gate line CG =0 V, and source wiring S =0 V. By setting selection gate line SG at 5 V, selection transistor 42 is rendered conductive, and the potential at n-type diffusion layer 12 becomes equal to that at bit line BL, i.e., 1 V. In this situation, when electrons are pre-injected into floating gate electrode 16, memory transistor 41 is not rendered conductive, this being due to threshold voltage V.sub.TH having been increased. For this reason, no current flows between bit line BL and source wiring S, and hence the potential at bit line BL is kept at 1 V. On the other hand, when the electrons are discharged from floating gate electrode 16, memory transistor 41 is rendered conductive, due to threshold voltage V.sub.TH being decreased. In these circumstances, current flows between bit line BL and source wiring S, and the potential at bit line BL becomes equal to that at source wiring S, i.e., 0 V. More specifically, logic "1" or "0" level is determined by amplifying the potential difference between 1 V and 0 V at bit line BL, using a sense amplifier (not shown) connected to bit line BL.
However, the problem which then arises is that the potential difference between 1 V and 0 V at bit line BL becomes amplified by the sense amplifier. That is, logic levels must be determined from the amplified potential difference.
The reason the potential at bit line BL must be limited to as low as 1 V and not increased up to 5 V in the read mode will now be explained below.
If bit line BL is set at 5 V in the read mode, the potential at n-type diffusion layer 12 becomes almost 5 V. As a result, an electric field generated by the potential difference between 0 V of control gate line CG and 5 V of n-type diffusion layer 12 is applied to thin insulating film 17 through floating gate electrode 16. In other words, this electric field is applied in the same direction as that in the write mode (electron discharge mode). The only difference, in this case, is that the intensity of this electric field is lower than that in the write mode. Consequently, if a cell in which electrons are injected is set in the read mode for a long period of time, the injected electrons are gradually discharged from floating gate electrode 16 because of the tunnel effect. As a result, threshold voltage V.sub.TH gradually decreases, which may give rise to a logical operation error occurring after a certain period of time. Such a phenomenon is known as a soft write (insufficient write) phenomenon. The retentivity of data as a function of time, in the event of a soft write phenomenon occurring is known as the read retention characteristic (data retentivity in the read mode).
To improve the read retention characteristic, the potential at bit line BL in thread mode can be lowered. However, in the read mode, the potential difference between an electron injection cell and an electron discharge cell becomes small, thereby degrading the logical margin. For this reason, in the conventional technique, bit line BL is set at about 1 V to sufficiently improve the read retention characteristic. On the other hand, a small logical margin is compensated for by using a high-performance sense amplifier or the like, and hence the sense amplifier is overloaded.
Accordingly, in the conventional technique, since the sense amplifier is overloaded, various problems are posed as follows. The arrangement of the sense amplifier is complicated, and the chip area of semiconductor memory is increased when the sense amplifier is formed into an integrated circuit. The increase in the chip area leads to an increase in manufacturing cost. In addition, the margin of operational power source voltage in the read mode is reduced, and especially, operation performance in a low-voltage range is degraded. Furthermore, a constant voltage source is required to apply an intermediate voltage of 1 V to bit line BL. If a circuit for generating such an intermediate voltage is incorporated in the sense amplifier, a current consumption is increased and this is disadvantageous in terms of power consumption. Finally, as the sense amplifier becomes complicated, the access time is increased.